With continuous shrinking of minimal feature size, leakage current is expected to become a major challenge for future complementary metal oxide silicon (CMOS) designs. Although each is about 10% of total chip power for the current generation of CMOS technology, the number is expected to rise to 50% for next generation techniques. The increasing leakage current not only poses a problem for battery powered devices, such as mobile and hand-held electronics, it is increasingly critical for active operation as it is becoming a higher percentage of total power.
Most of the leakage estimation and reduction techniques have focused on sub-threshold leakage due to the lowering of the power supply voltage and the accompanying reduction of the threshold voltage. With the reduction of the gate oxide thickness, the gate leakage current can no longer be ignored. Gate leakage is on a trend to become comparable to the sub-threshold leakage. An accurate full chip leakage estimation needs to consider both gate and sub-threshold leakage.
Methods to estimate the full chip leakage have been reported in several publications. The authors of one publication use a linear regression model to estimate full chip leakage based on the gate count in the application specific integrated circuit (ASIC) environment. In another publication, a method is proposed to include the effect of width in die process variation. It is known that the leakage current has strong dependency on the environmental factors, such as channel temperature, power supply voltage (Vdd) and workload. The leakage power has a near linear dependency on temperature, for example, a 30° C. change in temperature will affect the leakage by 30%. However, leakage power's dependency on Vdd is more exponential, whereby a 20% fluctuation in Vdd may affect the leakage power by more than a factor of two.
Chip designers have used empirical methods to estimate leakage power which assumes a uniform temperature and Vdd distribution across the whole chip. However, in today's complex industrial designs, both temperature and Vdd fluctuations have very strong locality, i.e., they are not uniform across the chip. The exact amount of these fluctuations at certain locations depends on the distribution of the transistors and decoupling capacitors, the workload, as well as the quality of the power grid and package design. Leakage also depends on circuit topology as well as process parameters. Empirical methods in full chip leakage estimation are too simplistic thus inaccurate.
Modern ICs used to implement computer and other data processing functions usually have circuit macros whose performance determines the processing power of the IC. These timing-critical circuit macros may only constitute 20% of the total circuits for the function of the IC. The other 80% of the circuits (timing-noncritical) are not as timing or speed dependent. However, leakage power is primarily dependent on the logic states of nodes, IC power supply voltage, temperature, and process variables. Therefore, the timing-noncritical circuitry may be dissipating more leakage power than is necessary. If the leakage power for the timing-noncritical circuitry could be reduced, then the excess power margin may be used to increase the performance of the timing-critical circuitry while keeping overall chip power within a desired limit. To do this, leakage power needs to be considered during the design process. Furthermore, the chip designers need to know how leakage power varies with process, feature size, and environmental factors so that design tradeoffs may be done that are most effective in reducing leakage power.
There is, therefore, a need for a method to determine average leakage power sensitivities for circuit macros that are independent of circuit state as well as a method for using leakage power sensitivities in the IC design process to optimize the IC.